SAME 2008 FORUM : OCTOBER 1 & 2, 2008

 
9:00 - 9:30 WELCOME Breakfast and Registration
  Auditorium Hall
9:30 - 9:35 Welcome at the SAME 2008 Forum : Official Opening • 5 min
EXHIBITION
9:35 - 10:20 KEYNOTE SPEAKER • Dennis BUSS, Texas Instruments • 45 min
10:20 - 11:50 EXECUTIVE PANEL • 90 min
GREEN ELECTRONICS: INNOVATION IN THE ENVIRONMENTAL REVOLUTION
11:50 - 13:00 LUNCH
  Auditorium Room 121
13:00 - 14:30 START-UPS PANEL • 90 min

TUTORIAL 1 • 1h30

(Chairman: Philippe Lorenzini, Polytech'Nice Sophia Antipolis)

PLL fundamentals for Circuit and System Design
Texas Instruments and Polytech'Nice Sophia Antipolis

14:30 BREAK
15:00 - 16:30

TUTORIAL 2 • 1h30

(Chairman: Xavier Duperthuy, NXP Semiconductors)
SESSION 1 • 1h30 : PLL

(Chairman: Olivier Omedes, Cadence)
15:00

Statistical Static Timing Analysis (SSTA)
Cadence Design Systems


 Fully integrated, high performance triple SD PLL(2.2Ghz to 4.4Ghz) with minimized interaction
Entropic Communications
15:30 Ku-BAND PLL Functional Blocks
University Modena, University Nice
16:00 PLL based synthesizer for KA band satellite receiver
Entropic Communications
16:30 - 17:00 BREAK
17:00 - 17:30
SESSION 2 - 1h30
LOW POWER, DESIGN TOOLS & METHODOLOGY - Part 1

(Chairman: Sylvan Dissoubray, Esterel EDA Technologies)


SESSION 3 - 1h30 : RF & MIXED SIGNAL DESIGN

(Chairman: Lorenzo Carpineto, Entropic)
17:00 Scalable TLM Modeling for Low-Power Design
Mentor Graphics 		Ku-BAND Receiver Functional Blocks
University Modena, University Nice
17:30 Power Management: From a Textual-Centric to a Model-Centric Perspective
Texas Instruments 		RF System in Package Design for portability between suppliers and technology platforms
Insight Sip
18:00 Advanced Verification of Low Power Designs
Mentor Graphics 		Current Reference without Inversion Constraint for Low Power Applications by using CAD Tool
Atmel, IM2NP, ISEN
18:30 CLOSE
18:30 - 19:15 START-UPS' COCKTAIL & REMISE IPOD SGBS
19:45 - 23:00 SAME DINNER PARTY & START-UP AWARD


 
9:00 - 9:15 Breakfast and Registration
  Auditorium Hall
9:15 - 10:15 KEYNOTE SPEAKER : Ted VUCUREVICH, Cadence • 45 min
EXHIBITION
10:15 - 11:15 TECHNICAL PANEL • 60 min
Low Power: Engineering fad or Key Success Factor for the industry?
  Auditorium Room 121
11:15 - 12:15 SPECIAL EVENT :

"SOLAR IMPULSE"
www.solarimpulse.com/en/index.php

(Chairman: Nicolas Coma, Altran)
SESSION 4 • 1h

LOW POWER PROCESSOR

(Chairman: Rob Mathews)
11:15 Processor Cores and Architectures for Low Energy ASICs
Cambridge Consultants
11:45 High-Performance and low power combination in the ARM Cortex-A9 Mpcore
ARM
12:15 - 13:30 LUNCH
13:30 - 14:30
SESSION 5 • 1h

LOW POWER EMBEDDED SOFTWARE

(Chairman: Christophe Evrard, ARM)

TUTORIAL 3 • 1h

(Chairman: Gabriele Zarri)

Efficient Prototyping of Analog
And Mixed Signal Integrated Circuits
austriamicrosystems

13:30 Mixed Scheduling for improved resource utilization
and energy consumption in real-time multiprocessor systems
LEAT, CNRS
14:00 Low Power Management of a Component based
Application over Embedded (Symetric) Multiprocessor Plateform
Thales Communications, LEAT
14:30 - 15:00 BREAK
15:00 - 16:30
SESSION 6 • 1h30

LOW POWER, DESIGN TOOLS & METHODOLOGY - Part 2

(Chairman: Tony Takeshian, Ikanos)

TUTORIAL 4 • 1h30

(Chairman: Pascal Jullien, Scaleo Chip)

Process Variability and FPGAs
Imperial college London

15:00 ATPG techniques to manage power during scan test
Cadence
15:30 An IP into SoC Hierarchical Integrator
ARM
16:00 Timing-Preserved Methodology for Interconnect Yield Optimization
and ECO Routing
Cadence
16:30 BEST AWARDS : BEST PAPER • BEST POSTER End Exhibition
17:00
 COCKTAIL PARTY & CONCLUSION
  



Frédéric Choquet Texas Instruments and Gilles Jacquemod Polytech’ Nice Sophia Antipolis
Chairman: Philippe LORENZINI, Polytech’ Nice Sophia Antipolis

Pierrick Pedron, Cadence Design Systems
Chairman: Xavier DUPERTHUY, NXP Semiconductor

Chairman: Olivier OMEDES, Cadence
   
  15:00 • Fully integrated, high performance triple SD PLL(2.2Ghz to 4.4Ghz) with minimized interaction:
Stefano Cipriani, Eric Duvivier, Gianni Puccio, Lorenzo Carpineto, Biagio Bisanti, Francesco Coppola, Martin Alderton*, Jeremy Goldblatt* (Entropic Communications, Sophia Antipolis, France and * San Diego, USA)
  15:30 • Ku-BAND PLL Functional Blocks:
F. Ducati, F. Chiesi, D. Dermit, G. Manni, P. Lucchi, F.B. Abdeljelil*, F. Sala, M. Borgarino, G. Jacquemod* (University of Modena and Reggio E., Italy and * University of Nice, France)
  16:00 • PLL based synthesizer for KA band satellite receiver:
Stefano Cipriani, Eric Duvivier, Gianni Puccio, Lorenzo Carpineto, Biagio Bisanti, Francesco Coppola, MarcoPifferi, Lysienne Koechlin (Entropic Communications, Sophia Antipolis, France)

Chairman: Sylvan DISSOUBRAY, Esterel EDA Technologies
   
  17:00 • Scalable TLM Modeling for Low-Power Design:
Alon Wintergreen and Zvika Amir (Mentor Graphics Corporation, Herzliya Pituah, Israel)
  17:30 • Power Management: From a Textual-Centric to a Model-Centric Perspective:
Lionel Blanc, (Texas Instruments, Villeneuve-Loubet, France)
  18:00 • Advanced Verification of Low Power Designs:
Stephan Bailey, Gabriele Chidolue* (Mentor Graphics USA and * UK)

Chairman:Lorenzo CARPINETO, Entropic
   
  17:00 • Ku-BAND Receiver Functional Blocks:
F.Ducati, F.Chiesi, N.Corciulo, M.Borgarino, G.Jacquemod* (University of Modena and Reggio E., Italy and * University of Nice, France)
  17:30 • RF System in Package Design for portability between suppliers and technology platforms:
Christopher Barratt (Insight SiP, Sophia Antipolis, France)
  18:00 •Current Reference without Inversion Constraint for Low Power Applications by using CAD Tool:
Francois Rudolff, Gaetan Bracmard and * Edith Kussener (ATMEL, Rousset and * IM2NP, ISEN_TOULON, Toulon, France)


Peter Pann, Austriamicrosystems
Chairman:Gabriele ZARRI

Peter Y. K. Cheung & Pete Sedcole, Imperial College London
Chairman:Pascal JULLIEN, Scaleo Chip

Chairman: Rob MATHEWS
   
  11:15 • Processor Cores and Architectures for Low Energy ASICS:
Chris Turner (Cambridge Consultants, Cambridge UK)
  11:45 • High-Performance and low power combination in the ARM Cortex-A9 MPcore:
Stéphane Brochier (ARM Sophia Antipolis, France)

Chairman: Christophe EVRARD, ARM
   
  13:30 • Mixed Scheduling for improved resource utilization and energy consumption in real-time multiprocessor systems:
Muhammad Khurram BHATTI, Muhammad FAROOQ, Cecile BELLEUDY, Michel AUGUIN (LEAT-CNRS, University of Nice-Sophia Antipolis, France)
  14:00 • Low Power Management of a Component based Application over Embedded (Symetric) Multiprocessor Plateform:
Thibault Dupont, Vincent Seignole, Cécile Belleudy*, Michel Auguin* (Thales Communication and * LEAT Colombes, France)

Chairman: Tony TAKESHIAN, Ikanos
   
  15:00 • ATPG techniques to manage power during scan test:
Richard Illman, Patrick Gallagher, Brion Keller (Cadence Design Systems, Inc., Livingston, Scotland)
  15:30 • An IP into SoC Hierarchical Integrator:
Mikhail Baklashov (ARM, Inc., Sunnyvale, CA USA)
  16:00 • Timing-Preserved Methodology for Interconnect Yield Optimization and ECO Routing:
Carpentier Benoit (Cadence Design Systems, Inc. Sophia Antipolis, France)


Updated, July 10th 2008
• Contact : same@cote-azur.cci.fr