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SOPHIA ANTIPOLIS FORUM ON MICROELECTRONICS
NOVEMBER
14th & 15th, 2001
PROGRAMME
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WEDNESDAY NOVEMBER 14Th |
| 9.00 |
WELCOME, BREAKFAST AND REGISTRATION
Speaker : Jacques Olivier PIEDNOIR, Cadence Design Systems,
General Chair SAME 2001 |
| 9.30
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TUTORIAL 1
xDSL Data
Transmission
Jean-Yves MICHEL
Centillium Communications |
TUTORIAL 2
Challenges of Physical Design of VDSM
CHIP
Jacques-Olivier PIEDNOIR
Cadence Design Systems
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12.30 LUNCH |
| 14.00 |
TUTORIAL 3
Bluethooth
Michel EFTIMAKIS
& Dominique CHOMIENNE
Newlogic
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TUTORIAL 4
The Esterel Studio Technology
Gérard BERRY
Esterel Technologies |
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THURSDAY NOVEMBER
15th |
| 9.00 |
WELCOME, BREAKFAST AND REGISTRATION |
| 9.30 |
SESSION 1
ANALOG DESIGN |
SESSION 2
EDA/DESIGN METHODOLOGY
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| 11.30 |
KEY NOTE by André JOLIVET - Stepmind |
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12.00 LUNCH |
| 14.00 |
SESSION 3
MEMORY DESIGN
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SESSION 4
TEST & VERIFICATION
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15.30 COFFEE BREAK |
| 16.00
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SESSION 5
CIRCUIT DESIGN |
SESSION 6
MASK FINISHING
&
PHYSICAL VERIFICATION
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17.30 COCKTAIL PARTY
& CONCLUSION
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18.30 SAME CLOSURE |
November, 15th
2001
10.00
: Session 1 : ANALOG DESIGN
Chairman : Yves
LEDUC, Texas Instruments
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Mixed analog/MEMS
prototyping using Cadence Spectre simulator : D. Moulinier,
M.P. Brutails, S. Bergeon (MEMSCAP). Rigth
click and save target as to download Paper
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A Global Methodology
for High-Speed continuous-time Sigma-Delta converters design
: P. Benabes, A. Gauthier, R. Kielbasa (SUPELEC). Rigth
click and save target as to download Paper
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Accurate Hi-Speed
Simulation of Electro-magnetic Effects in Real-Life Circuits;
A Mobile Phone Power Amplifier Module and an FM Radio Tuner
PCB : Jan Niehof, (PHILIPS RESEARCH). Rigth click and save target as to download Paper
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Adapt, an interactive
tool for analog synthesis : M. Kole, E. van Duren, R. Hermans,
M. Sevat, J. ter Maten, J. van Gerwen, P. Bachrach (PHILIPS
ELECTRONICS N. V.). Rigth click and save target as to download Paper
10.00
: Session 2 : EDA / DESIGN METHODOLOGY
Chairman : Arnold
GINETTI, Cadence
14.00
: Session 3 : MEMORY DESIGN
Chairman :
Jean-Christophe VIAL, Infineon Technologies
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A cookbook approach
for comparing objectively memory generators : A. Bonzo, F. Renoux
(DOLPHIN). 1-Rigth click and save target as to download Paper 2-Rigth click and save target as to download Paper 3-Rigth click and save target as to download Paper 4-Rigth click and save target as to download Paper
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EEPROM Programming
Signal Study Reliability and Quickness : P. Canet, R. Bouchakour,
N. Harabech, J. Razafindramora; P. Boivin, J.M. Mirabel (L2MP,
ST-Microelectronics). Rigth click and save target as to download Paper
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EEPROM Cell Negative
Voltage Programming Consumption and Reliability Impact : N.
Harabech, R. Bouchakour, P. Canet, P. Boivin, J.M. Mirabel (L2MP,
ST-Microelectronics). Rigth click and save target as to download Paper
14.00
: Session 4 : TEST & VERIFICATION
Chairman : Pierre
BRICAUD, Mentor Graphics
16.00
: Session 5 : CIRCUIT DESIGN
Chairman : Michel
Eftimakis, Newlogic
16.00
: Session 6 : MASK FINISHING & PHYSICAL VERIFICATION
Chairman : Xavier
Duperthuy, Avant !
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