October 6, 2010: 15:30 – 17:00 (90 min)

Traditionally the packaging of semiconductor dies has been seen as a simple operation that is carried out once the dies have been produced with a low level of interaction between the package and die design. Today this situation is no longer true since the need to miniaturize systems and keep connection distances short is leading to a wide variety of new and advanced packaging techniques. These techniques include advanced wafer level packaging, flip chip and wire-bond die stacking for System in Package (SiP) and even higher levels of integration involving direct 3D die stacking with Through Silicon Vias (TSV) and embedding dies in organic substrates.

The panel session is aimed at familiarizing the IC hardware and software design community with the technologies, challenges and time lines for this wide-ranging 3D SiP and Advanced Packaging phenomenon. The panel will include experts from as many different facets of the SiP arena as possible and will include short presentations from each participant followed by a discussion on the relative merits, time-lines and issues for each technology. The debate will include view-points from the technology R&D community, the large scale IDM user, the smaller fab-less start-up, the EDA community, the design services area and a third party contract manufacturing contractor.